IEEE

FPGA Based AI Inference Accelerator for Low-End Embedded Systems

Aim: This research aims to develop a hardware accelerator to inference AI models for low-end embedded platforms using FPGAs as they are reconfigurable, have parallel and real-time processing ...
IEEE

FPGA IP Core for DC Motor Control With Adaptive Neural Network PID Tuning, and High-Resolution Encoder Interface

Abstract: Traditional proportional integral derivative (PID) falls short for precise control of DC motor speed under changing conditions. This paper presents a novel FPGA based IP (intellectual ...
GitHub

An FPGA Accelerator for Transformer Inference

We accelerated a BERT layer across two FPGAs, partitioned into four pipeline stages. We conduct three levels of optimization using Vitis HLS and report runtimes. The accelerator implements a ...